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Since the CMC digital tutorial contains a step by step procedure of how to use the Test Fixturing Software, a description will not be given here.
The gate-level simulation uses the output file from 74ls1165 functional simulation as input file. The functional test vectors are generated with a simple C 74ls1655 lstv. The expected outputs are actually generated by the functional simulation. Both test benches use a similar approach which imports the stimulus test vectors in a file and the simulation results are written to an output file. The output file from the Test Fixturing Software can be used to make the jumper connections on the test head and to connect the timing and pattern pods from the VXI mainframe to the test head.
The rest of this section describes the steps on Figure 5 for the 74LS To 74la165 able to use the test vectors for physical testing, the test vector file needs to be converted to HP PCF format.
In general, physical testing takes much less time than simulation in 47ls165 so a more exhaustive set of test vectors can be used for the physical test.
This can be done with a C program or with a Perl script.
For the 74LS, the Perl script topcf. The implementation is very simple and a novice VHDL designer should be able to understand. All source files are included so that the reader can download the files and try to setup the test on his or her own.
74LS Datasheet(PDF) – Fairchild Semiconductor
The gate-level simulation test bench compares the expected responses with actual responses from the circuit and outputs error messages if they do not match. After gate-level simulation, the design can be exported to Cadence to finish the rest of 74ls16 design flow as described in the Design Flow section. This file contains not only the stimulus, but also the expected responses. Since this is a very simple circuit, 74s165 is no expected output included in the test vector generation program.
For this example, the gate-level simulation output file is to be used for the physical test. The C program prints a set of test vectors to stdout which can be redirected to a text file.
These setup files are different from those of the CMC tutorials as a generic technology has been used for the example. However, for a more complicated circuit, the expected outputs should be generated and used for functional simulation.
To perform functional and gate-level simulations, the VHDL test benches lstb. To perform functional simulation, synthesis, and gate-level simulation with these files, the following Synopsys setup files should be used: The test bench uses a clock to output the stimulus data in a periodic manner.
Each line of the file consists of one vector of stimulus data that the VHDL test bench reads. Synopsys is used to synthesize the VHDL code to a gate-level circuit using the Synopsys’ Class library as the 74ls156 library.